From 0a49062a02045e920d03d317ce42fb0ea699688a Mon Sep 17 00:00:00 2001 From: Chris Drake Date: Wed, 30 Jan 2013 22:02:31 -0800 Subject: [PATCH] Add Verilog/SystemVerilog filename extensions Most Verilog files use the *.vh extension for header files. Since the IEEE 1800-2009 SystemVerilog standard, it is common for hardware and verification files written using the newer language constructs to use the *.sv extension for design elements, and *.svh for headers. --- lib/linguist/languages.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/linguist/languages.yml b/lib/linguist/languages.yml index c12becd6..3522b140 100644 --- a/lib/linguist/languages.yml +++ b/lib/linguist/languages.yml @@ -1192,6 +1192,10 @@ Verilog: lexer: verilog color: "#848bf3" primary_extension: .v + extensions: + - .vh + - .sv + - .svh VimL: type: programming