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Support of SystemVerilog
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Paul Chaignon
216
samples/SystemVerilog/endpoint_phy_wrapper.svh
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216
samples/SystemVerilog/endpoint_phy_wrapper.svh
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module endpoint_phy_wrapper
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(
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input clk_sys_i,
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input clk_ref_i,
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input clk_rx_i,
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input rst_n_i,
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IWishboneMaster.master src,
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IWishboneSlave.slave snk,
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IWishboneMaster.master sys,
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output [9:0] td_o,
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input [9:0] rd_i,
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output txn_o,
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output txp_o,
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input rxn_i,
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input rxp_i
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);
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wire rx_clock;
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parameter g_phy_type = "GTP";
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wire[15:0] gtx_data;
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wire [1:0]gtx_k;
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wire gtx_disparity;
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wire gtx_enc_error;
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wire [15:0] grx_data;
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wire grx_clk;
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wire [1:0]grx_k;
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wire grx_enc_error;
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wire [3:0] grx_bitslide;
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wire gtp_rst;
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wire tx_clock;
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generate
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if(g_phy_type == "TBI") begin
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assign rx_clock = clk_ref_i;
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assign tx_clock = clk_rx_i;
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wr_tbi_phy U_Phy
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(
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.serdes_rst_i (gtp_rst),
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.serdes_loopen_i(1'b0),
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.serdes_prbsen_i(1'b0),
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.serdes_enable_i(1'b1),
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.serdes_syncen_i(1'b1),
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.serdes_tx_data_i (gtx_data[7:0]),
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.serdes_tx_k_i (gtx_k[0]),
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.serdes_tx_disparity_o (gtx_disparity),
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.serdes_tx_enc_err_o (gtx_enc_error),
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.serdes_rx_data_o (grx_data[7:0]),
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.serdes_rx_k_o (grx_k[0]),
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.serdes_rx_enc_err_o (grx_enc_error),
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.serdes_rx_bitslide_o (grx_bitslide),
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.tbi_refclk_i (clk_ref_i),
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.tbi_rbclk_i (clk_rx_i),
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.tbi_td_o (td_o),
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.tbi_rd_i (rd_i),
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.tbi_syncen_o (),
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.tbi_loopen_o (),
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.tbi_prbsen_o (),
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.tbi_enable_o ()
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);
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end else if (g_phy_type == "GTX") begin // if (g_phy_type == "TBI")
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wr_gtx_phy_virtex6
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#(
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.g_simulation(1)
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) U_PHY
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(
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.clk_ref_i(clk_ref_i),
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.tx_clk_o (tx_clock),
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.tx_data_i (gtx_data),
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.tx_k_i (gtx_k),
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.tx_disparity_o (gtx_disparity),
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.tx_enc_err_o(gtx_enc_error),
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.rx_rbclk_o (rx_clock),
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.rx_data_o (grx_data),
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.rx_k_o (grx_k),
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.rx_enc_err_o (grx_enc_error),
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.rx_bitslide_o (),
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.rst_i (!rst_n_i),
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.loopen_i (1'b0),
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.pad_txn_o (txn_o),
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.pad_txp_o (txp_o),
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.pad_rxn_i (rxn_i),
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.pad_rxp_i (rxp_i)
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);
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end else if (g_phy_type == "GTP") begin // if (g_phy_type == "TBI")
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assign #1 tx_clock = clk_ref_i;
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wr_gtp_phy_spartan6
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#(
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.g_simulation(1)
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) U_PHY
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(
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.gtp_clk_i(clk_ref_i),
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.ch0_ref_clk_i(clk_ref_i),
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.ch0_tx_data_i (gtx_data[7:0]),
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.ch0_tx_k_i (gtx_k[0]),
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.ch0_tx_disparity_o (gtx_disparity),
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.ch0_tx_enc_err_o(gtx_enc_error),
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.ch0_rx_rbclk_o (rx_clock),
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.ch0_rx_data_o (grx_data[7:0]),
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.ch0_rx_k_o (grx_k[0]),
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.ch0_rx_enc_err_o (grx_enc_error),
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.ch0_rx_bitslide_o (),
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.ch0_rst_i (!rst_n_i),
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.ch0_loopen_i (1'b0),
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.pad_txn0_o (txn_o),
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.pad_txp0_o (txp_o),
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.pad_rxn0_i (rxn_i),
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.pad_rxp0_i (rxp_i)
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);
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end // else: !if(g_phy_type == "TBI")
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endgenerate
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wr_endpoint
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#(
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.g_simulation (1),
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.g_pcs_16bit(g_phy_type == "GTX" ? 1: 0),
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.g_rx_buffer_size (1024),
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.g_with_rx_buffer(0),
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.g_with_timestamper (1),
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.g_with_dmtd (0),
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.g_with_dpi_classifier (1),
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.g_with_vlans (0),
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.g_with_rtu (0)
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) DUT (
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.clk_ref_i (clk_ref_i),
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.clk_sys_i (clk_sys_i),
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.clk_dmtd_i (clk_ref_i),
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.rst_n_i (rst_n_i),
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.pps_csync_p1_i (1'b0),
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.phy_rst_o (),
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.phy_loopen_o (),
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.phy_enable_o (),
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.phy_syncen_o (),
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.phy_ref_clk_i (tx_clock),
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.phy_tx_data_o (gtx_data),
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.phy_tx_k_o (gtx_k),
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.phy_tx_disparity_i (gtx_disparity),
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.phy_tx_enc_err_i (gtx_enc_error),
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.phy_rx_data_i (grx_data),
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.phy_rx_clk_i (rx_clock),
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.phy_rx_k_i (grx_k),
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.phy_rx_enc_err_i (grx_enc_error),
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.phy_rx_bitslide_i (5'b0),
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.src_dat_o (snk.dat_i),
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.src_adr_o (snk.adr),
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.src_sel_o (snk.sel),
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.src_cyc_o (snk.cyc),
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.src_stb_o (snk.stb),
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.src_we_o (snk.we),
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.src_stall_i (snk.stall),
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.src_ack_i (snk.ack),
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.src_err_i(1'b0),
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.snk_dat_i (src.dat_o[15:0]),
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.snk_adr_i (src.adr[1:0]),
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.snk_sel_i (src.sel[1:0]),
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.snk_cyc_i (src.cyc),
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.snk_stb_i (src.stb),
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.snk_we_i (src.we),
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.snk_stall_o (src.stall),
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.snk_ack_o (src.ack),
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.snk_err_o (src.err),
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.snk_rty_o (src.rty),
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.txtsu_ack_i (1'b1),
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.rtu_full_i (1'b0),
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.rtu_almost_full_i (1'b0),
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.rtu_rq_strobe_p1_o (),
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.rtu_rq_smac_o (),
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.rtu_rq_dmac_o (),
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.rtu_rq_vid_o (),
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.rtu_rq_has_vid_o (),
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.rtu_rq_prio_o (),
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.rtu_rq_has_prio_o (),
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.wb_cyc_i(sys.cyc),
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.wb_stb_i (sys.stb),
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.wb_we_i (sys.we),
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.wb_sel_i(sys.sel),
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.wb_adr_i(sys.adr[7:0]),
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.wb_dat_i(sys.dat_o),
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.wb_dat_o(sys.dat_i),
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.wb_ack_o (sys.ack)
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);
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endmodule // endpoint_phy_wrapper
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7
samples/SystemVerilog/fifo.sv
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7
samples/SystemVerilog/fifo.sv
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@@ -0,0 +1,7 @@
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module fifo (
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input clk_50,
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input clk_2,
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input reset_n,
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output [7:0] data_out,
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output empty
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);
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18
samples/SystemVerilog/priority_encoder.sv
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18
samples/SystemVerilog/priority_encoder.sv
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// http://hdlsnippets.com/parameterized_priority_encoder
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module priority_encoder #(parameter INPUT_WIDTH=8,OUTPUT_WIDTH=3)
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(
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input logic [INPUT_WIDTH-1:0] input_data,
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output logic [OUTPUT_WIDTH-1:0] output_data
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);
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int ii;
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always_comb
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begin
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output_data = 'b0;
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for(ii=0;ii<INPUT_WIDTH;ii++)
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if (input_data[ii])
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output_data = ii[OUTPUT_WIDTH-1:0];
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end
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endmodule
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