Support of SystemVerilog

2025-12-08 20:38:47 +00:00 · 2014-02-21 17:48:24 +01:00
parent a34398eb92
commit 28a2b39a55
4 changed files with 249 additions and 0 deletions
--- a/samples/SystemVerilog/fifo.sv
+++ b/samples/SystemVerilog/fifo.sv
@@ -0,0 +1,7 @@
+module fifo (
+    input           clk_50,
+    input           clk_2,
+    input           reset_n,
+    output [7:0]    data_out,
+    output          empty
+);