New Verilog and Coq sample files added

New Verilog examples and Coq examples for additional training have
been added since linguist is currently failing Coq/Verilog recognition
tasks (see #201). In case it wasn't obvious, linguist will not
currently pass these new, added test cases.

samples/verilog/pipeline_registers.v

@@ -0,0 +1,82 @@
+////////////////////////////////////////////////////////////////////////////////
+// Original Author: Schuyler Eldridge
+// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
+// pipeline_registers.v
+// Created: 4.4.2012
+// Modified: 4.4.2012
+//
+// Implements a series of pipeline registers specified by the input
+// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
+// size of the signal passed through each of the pipeline
+// registers. NUMBER_OF_STAGES is the number of pipeline registers
+// generated. This accepts values of 0 (yes, it just passes data from
+// input to output...) up to however many stages specified.
+// Copyright (C) 2012 Schuyler Eldridge, Boston University
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+////////////////////////////////////////////////////////////////////////////////
+`timescale 1ns / 1ps
+module pipeline_registers
+  (
+   input                      clk,
+   input                      reset_n,
+   input [BIT_WIDTH-1:0]      pipe_in,
+   output reg [BIT_WIDTH-1:0] pipe_out
+   );
+
+  // WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
+  // LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
+  // OVERWRITTEN!
+  parameter 
+    BIT_WIDTH         = 10,
+    NUMBER_OF_STAGES  = 5;
+
+  // Main generate function for conditional hardware instantiation
+  generate
+    genvar                                 i;
+    // Pass-through case for the odd event that no pipeline stages are
+    // specified.
+    if (NUMBER_OF_STAGES == 0) begin
+      always @ *
+        pipe_out = pipe_in;
+    end
+    // Single flop case for a single stage pipeline
+    else if (NUMBER_OF_STAGES == 1) begin
+      always @ (posedge clk or negedge reset_n)
+        pipe_out <= (!reset_n) ? 0 : pipe_in;
+    end
+    // Case for 2 or more pipeline stages
+    else begin
+      // Create the necessary regs
+      reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
+      // Create logic for the initial and final pipeline registers
+      always @ (posedge clk or negedge reset_n) begin
+        if (!reset_n) begin
+          pipe_gen[BIT_WIDTH-1:0] <= 0;
+          pipe_out                <= 0;
+        end
+        else begin
+          pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
+          pipe_out                <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
+        end
+      end
+      // Create the intermediate pipeline registers if there are 3 or
+      // more pipeline stages
+      for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
+        always @ (posedge clk or negedge reset_n)
+          pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
+      end
+    end
+  endgenerate
+  
+endmodule