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New Verilog and Coq sample files added
New Verilog examples and Coq examples for additional training have been added since linguist is currently failing Coq/Verilog recognition tasks (see #201). In case it wasn't obvious, linguist will not currently pass these new, added test cases.
This commit is contained in:
Schuyler Eldridge
175
samples/verilog/ps2_mouse.v
Executable file
175
samples/verilog/ps2_mouse.v
Executable file
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/*
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* PS2 Mouse Interface
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* Copyright (C) 2010 Donna Polehn <dpolehn@verizon.net>
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*
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* This file is part of the Zet processor. This processor is free
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* hardware; you can redistribute it and/or modify it under the terms of
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* the GNU General Public License as published by the Free Software
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* Foundation; either version 3, or (at your option) any later version.
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*
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* Zet is distrubuted in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Zet; see the file COPYING. If not, see
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* <http://www.gnu.org/licenses/>.
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*/
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module ps2_mouse (
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input clk, // Clock Input
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input reset, // Reset Input
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inout ps2_clk, // PS2 Clock, Bidirectional
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inout ps2_dat, // PS2 Data, Bidirectional
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input [7:0] the_command, // Command to send to mouse
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input send_command, // Signal to send
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output command_was_sent, // Signal command finished sending
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output error_communication_timed_out,
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output [7:0] received_data, // Received data
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output received_data_en, // If 1 - new data has been received
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output start_receiving_data,
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output wait_for_incoming_data
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);
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// --------------------------------------------------------------------
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// Internal wires and registers Declarations
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// --------------------------------------------------------------------
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wire ps2_clk_posedge; // Internal Wires
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wire ps2_clk_negedge;
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reg [7:0] idle_counter; // Internal Registers
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reg ps2_clk_reg;
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reg ps2_data_reg;
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reg last_ps2_clk;
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reg [2:0] ns_ps2_transceiver; // State Machine Registers
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reg [2:0] s_ps2_transceiver;
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// --------------------------------------------------------------------
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// Constant Declarations
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// --------------------------------------------------------------------
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localparam PS2_STATE_0_IDLE = 3'h0, // states
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PS2_STATE_1_DATA_IN = 3'h1,
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PS2_STATE_2_COMMAND_OUT = 3'h2,
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PS2_STATE_3_END_TRANSFER = 3'h3,
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PS2_STATE_4_END_DELAYED = 3'h4;
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// --------------------------------------------------------------------
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// Finite State Machine(s)
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// --------------------------------------------------------------------
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always @(posedge clk) begin
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if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
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else s_ps2_transceiver <= ns_ps2_transceiver;
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end
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always @(*) begin
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ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
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case (s_ps2_transceiver)
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PS2_STATE_0_IDLE:
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begin
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if((idle_counter == 8'hFF) && (send_command == 1'b1))
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ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
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else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
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ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
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else ns_ps2_transceiver = PS2_STATE_0_IDLE;
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end
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PS2_STATE_1_DATA_IN:
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begin
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// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
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if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
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else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
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end
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PS2_STATE_2_COMMAND_OUT:
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begin
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if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
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ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
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else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
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end
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PS2_STATE_3_END_TRANSFER:
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begin
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if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
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else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
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ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
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else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
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end
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PS2_STATE_4_END_DELAYED:
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begin
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if(received_data_en == 1'b1) begin
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if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
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else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
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end
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else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
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end
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default:
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ns_ps2_transceiver = PS2_STATE_0_IDLE;
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endcase
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end
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// --------------------------------------------------------------------
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// Sequential logic
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// --------------------------------------------------------------------
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always @(posedge clk) begin
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if(reset == 1'b1) begin
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last_ps2_clk <= 1'b1;
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ps2_clk_reg <= 1'b1;
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ps2_data_reg <= 1'b1;
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end
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else begin
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last_ps2_clk <= ps2_clk_reg;
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ps2_clk_reg <= ps2_clk;
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ps2_data_reg <= ps2_dat;
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end
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end
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always @(posedge clk) begin
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if(reset == 1'b1) idle_counter <= 6'h00;
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else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
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idle_counter <= idle_counter + 6'h01;
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else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
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idle_counter <= 6'h00;
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end
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// --------------------------------------------------------------------
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// Combinational logic
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// --------------------------------------------------------------------
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assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
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assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
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assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
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assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
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// --------------------------------------------------------------------
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// Internal Modules
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// --------------------------------------------------------------------
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ps2_mouse_cmdout mouse_cmdout (
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.clk (clk), // Inputs
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.reset (reset),
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.the_command (the_command),
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.send_command (send_command),
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.ps2_clk_posedge (ps2_clk_posedge),
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.ps2_clk_negedge (ps2_clk_negedge),
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.ps2_clk (ps2_clk), // Bidirectionals
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.ps2_dat (ps2_dat),
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.command_was_sent (command_was_sent), // Outputs
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.error_communication_timed_out (error_communication_timed_out)
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);
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ps2_mouse_datain mouse_datain (
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.clk (clk), // Inputs
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.reset (reset),
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.wait_for_incoming_data (wait_for_incoming_data),
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.start_receiving_data (start_receiving_data),
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.ps2_clk_posedge (ps2_clk_posedge),
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.ps2_clk_negedge (ps2_clk_negedge),
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.ps2_data (ps2_data_reg),
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.received_data (received_data), // Outputs
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.received_data_en (received_data_en)
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);
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endmodule
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