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55 lines
1.3 KiB
Verilog
Executable File
55 lines
1.3 KiB
Verilog
Executable File
/*
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* Copyright (c) 2009 Zeus Gomez Marmolejo <zeus@opencores.org>
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*
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* This file is part of the Zet processor. This processor is free
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* hardware; you can redistribute it and/or modify it under the terms of
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* the GNU General Public License as published by the Free Software
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* Foundation; either version 3, or (at your option) any later version.
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*
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* Zet is distrubuted in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Zet; see the file COPYING. If not, see
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* <http://www.gnu.org/licenses/>.
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*/
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module hex_display (
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input [15:0] num,
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input en,
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output [6:0] hex0,
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output [6:0] hex1,
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output [6:0] hex2,
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output [6:0] hex3
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);
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// Module instantiations
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seg_7 hex_group0 (
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.num (num[3:0]),
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.en (en),
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.seg (hex0)
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);
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seg_7 hex_group1 (
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.num (num[7:4]),
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.en (en),
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.seg (hex1)
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);
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seg_7 hex_group2 (
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.num (num[11:8]),
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.en (en),
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.seg (hex2)
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);
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seg_7 hex_group3 (
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.num (num[15:12]),
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.en (en),
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.seg (hex3)
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);
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endmodule
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