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46 lines
1.2 KiB
Verilog
Executable File
46 lines
1.2 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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// Copyright (C) 2008 Schuyler Eldridge, Boston University
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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module mux(opA,opB,sum,dsp_sel,out);
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input [3:0] opA,opB;
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input [4:0] sum;
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input [1:0] dsp_sel;
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output [3:0] out;
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reg cout;
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always @ (sum)
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begin
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if (sum[4] == 1)
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cout <= 4'b0001;
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else
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cout <= 4'b0000;
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end
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reg out;
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always @(dsp_sel,sum,cout,opB,opA)
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begin
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if (dsp_sel == 2'b00)
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out <= sum[3:0];
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else if (dsp_sel == 2'b01)
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out <= cout;
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else if (dsp_sel == 2'b10)
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out <= opB;
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else if (dsp_sel == 2'b11)
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out <= opA;
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end
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endmodule
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