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New Verilog examples and Coq examples for additional training have been added since linguist is currently failing Coq/Verilog recognition tasks (see #201). In case it wasn't obvious, linguist will not currently pass these new, added test cases.
83 lines
3.3 KiB
Verilog
Executable File
83 lines
3.3 KiB
Verilog
Executable File
////////////////////////////////////////////////////////////////////////////////
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// Original Author: Schuyler Eldridge
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// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
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// pipeline_registers.v
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// Created: 4.4.2012
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// Modified: 4.4.2012
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//
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// Implements a series of pipeline registers specified by the input
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// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
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// size of the signal passed through each of the pipeline
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// registers. NUMBER_OF_STAGES is the number of pipeline registers
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// generated. This accepts values of 0 (yes, it just passes data from
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// input to output...) up to however many stages specified.
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// Copyright (C) 2012 Schuyler Eldridge, Boston University
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module pipeline_registers
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(
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input clk,
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input reset_n,
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input [BIT_WIDTH-1:0] pipe_in,
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output reg [BIT_WIDTH-1:0] pipe_out
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);
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// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
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// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
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// OVERWRITTEN!
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parameter
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BIT_WIDTH = 10,
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NUMBER_OF_STAGES = 5;
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// Main generate function for conditional hardware instantiation
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generate
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genvar i;
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// Pass-through case for the odd event that no pipeline stages are
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// specified.
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if (NUMBER_OF_STAGES == 0) begin
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always @ *
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pipe_out = pipe_in;
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end
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// Single flop case for a single stage pipeline
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else if (NUMBER_OF_STAGES == 1) begin
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always @ (posedge clk or negedge reset_n)
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pipe_out <= (!reset_n) ? 0 : pipe_in;
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end
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// Case for 2 or more pipeline stages
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else begin
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// Create the necessary regs
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reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
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// Create logic for the initial and final pipeline registers
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always @ (posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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pipe_gen[BIT_WIDTH-1:0] <= 0;
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pipe_out <= 0;
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end
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else begin
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pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
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pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
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end
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end
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// Create the intermediate pipeline registers if there are 3 or
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// more pipeline stages
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for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
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always @ (posedge clk or negedge reset_n)
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pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
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end
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end
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endgenerate
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endmodule
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