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New Verilog examples and Coq examples for additional training have been added since linguist is currently failing Coq/Verilog recognition tasks (see #201). In case it wasn't obvious, linguist will not currently pass these new, added test cases.
71 lines
1.9 KiB
Verilog
Executable File
71 lines
1.9 KiB
Verilog
Executable File
////////////////////////////////////////////////////////////////////////////////
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// Original Author: Schuyler Eldridge
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// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
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// button_debounce.v
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// Created: 4.5.2012
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// Modified: 4.5.2012
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//
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// Testbench for button_debounce.v.
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//
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// Copyright (C) 2012 Schuyler Eldridge, Boston University
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module t_button_debounce();
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parameter
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CLK_FREQUENCY = 66000000,
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DEBOUNCE_HZ = 2;
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reg clk, reset_n, button;
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wire debounce;
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button_debounce
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#(
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.CLK_FREQUENCY(CLK_FREQUENCY),
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.DEBOUNCE_HZ(DEBOUNCE_HZ)
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)
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button_debounce
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(
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.clk(clk),
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.reset_n(reset_n),
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.button(button),
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.debounce(debounce)
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);
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initial begin
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clk = 1'bx; reset_n = 1'bx; button = 1'bx;
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#10 reset_n = 1;
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#10 reset_n = 0; clk = 0;
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#10 reset_n = 1;
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#10 button = 0;
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end
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always
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#5 clk = ~clk;
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always begin
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#100 button = ~button;
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#0.1 button = ~button;
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#0.1 button = ~button;
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#0.1 button = ~button;
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#0.1 button = ~button;
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#0.1 button = ~button;
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#0.1 button = ~button;
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#0.1 button = ~button;
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#0.1 button = ~button;
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end
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endmodule
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