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https://github.com/KevinMidboe/linguist.git
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314 lines
8.2 KiB
Verilog
Executable File
314 lines
8.2 KiB
Verilog
Executable File
/*
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* VGA top level file
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* Copyright (C) 2010 Zeus Gomez Marmolejo <zeus@aluzina.org>
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*
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* This file is part of the Zet processor. This processor is free
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* hardware; you can redistribute it and/or modify it under the terms of
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* the GNU General Public License as published by the Free Software
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* Foundation; either version 3, or (at your option) any later version.
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*
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* Zet is distrubuted in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Zet; see the file COPYING. If not, see
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* <http://www.gnu.org/licenses/>.
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*/
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module vga (
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// Wishbone signals
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input wb_clk_i, // 25 Mhz VDU clock
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input wb_rst_i,
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input [15:0] wb_dat_i,
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output [15:0] wb_dat_o,
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input [16:1] wb_adr_i,
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input wb_we_i,
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input wb_tga_i,
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input [ 1:0] wb_sel_i,
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input wb_stb_i,
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input wb_cyc_i,
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output wb_ack_o,
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// VGA pad signals
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output [ 3:0] vga_red_o,
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output [ 3:0] vga_green_o,
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output [ 3:0] vga_blue_o,
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output horiz_sync,
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output vert_sync,
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// CSR SRAM master interface
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output [17:1] csrm_adr_o,
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output [ 1:0] csrm_sel_o,
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output csrm_we_o,
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output [15:0] csrm_dat_o,
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input [15:0] csrm_dat_i
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);
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// Registers and nets
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//
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// csr address
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reg [17:1] csr_adr_i;
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reg csr_stb_i;
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// Config wires
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wire [15:0] conf_wb_dat_o;
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wire conf_wb_ack_o;
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// Mem wires
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wire [15:0] mem_wb_dat_o;
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wire mem_wb_ack_o;
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// LCD wires
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wire [17:1] csr_adr_o;
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wire [15:0] csr_dat_i;
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wire csr_stb_o;
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wire v_retrace;
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wire vh_retrace;
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wire w_vert_sync;
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// VGA configuration registers
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wire shift_reg1;
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wire graphics_alpha;
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wire memory_mapping1;
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wire [ 1:0] write_mode;
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wire [ 1:0] raster_op;
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wire read_mode;
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wire [ 7:0] bitmask;
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wire [ 3:0] set_reset;
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wire [ 3:0] enable_set_reset;
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wire [ 3:0] map_mask;
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wire x_dotclockdiv2;
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wire chain_four;
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wire [ 1:0] read_map_select;
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wire [ 3:0] color_compare;
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wire [ 3:0] color_dont_care;
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// Wishbone master to SRAM
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wire [17:1] wbm_adr_o;
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wire [ 1:0] wbm_sel_o;
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wire wbm_we_o;
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wire [15:0] wbm_dat_o;
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wire [15:0] wbm_dat_i;
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wire wbm_stb_o;
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wire wbm_ack_i;
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wire stb;
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// CRT wires
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wire [ 5:0] cur_start;
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wire [ 5:0] cur_end;
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wire [15:0] start_addr;
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wire [ 4:0] vcursor;
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wire [ 6:0] hcursor;
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wire [ 6:0] horiz_total;
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wire [ 6:0] end_horiz;
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wire [ 6:0] st_hor_retr;
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wire [ 4:0] end_hor_retr;
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wire [ 9:0] vert_total;
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wire [ 9:0] end_vert;
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wire [ 9:0] st_ver_retr;
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wire [ 3:0] end_ver_retr;
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// attribute_ctrl wires
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wire [3:0] pal_addr;
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wire pal_we;
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wire [7:0] pal_read;
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wire [7:0] pal_write;
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// dac_regs wires
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wire dac_we;
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wire [1:0] dac_read_data_cycle;
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wire [7:0] dac_read_data_register;
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wire [3:0] dac_read_data;
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wire [1:0] dac_write_data_cycle;
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wire [7:0] dac_write_data_register;
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wire [3:0] dac_write_data;
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// Module instances
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//
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vga_config_iface config_iface (
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i),
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.wb_dat_i (wb_dat_i),
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.wb_dat_o (conf_wb_dat_o),
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.wb_adr_i (wb_adr_i[4:1]),
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.wb_we_i (wb_we_i),
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.wb_sel_i (wb_sel_i),
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.wb_stb_i (stb & wb_tga_i),
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.wb_ack_o (conf_wb_ack_o),
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.shift_reg1 (shift_reg1),
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.graphics_alpha (graphics_alpha),
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.memory_mapping1 (memory_mapping1),
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.write_mode (write_mode),
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.raster_op (raster_op),
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.read_mode (read_mode),
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.bitmask (bitmask),
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.set_reset (set_reset),
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.enable_set_reset (enable_set_reset),
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.map_mask (map_mask),
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.x_dotclockdiv2 (x_dotclockdiv2),
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.chain_four (chain_four),
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.read_map_select (read_map_select),
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.color_compare (color_compare),
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.color_dont_care (color_dont_care),
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.pal_addr (pal_addr),
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.pal_we (pal_we),
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.pal_read (pal_read),
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.pal_write (pal_write),
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.dac_we (dac_we),
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.dac_read_data_cycle (dac_read_data_cycle),
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.dac_read_data_register (dac_read_data_register),
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.dac_read_data (dac_read_data),
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.dac_write_data_cycle (dac_write_data_cycle),
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.dac_write_data_register (dac_write_data_register),
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.dac_write_data (dac_write_data),
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.cur_start (cur_start),
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.cur_end (cur_end),
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.start_addr (start_addr),
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.vcursor (vcursor),
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.hcursor (hcursor),
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.horiz_total (horiz_total),
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.end_horiz (end_horiz),
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.st_hor_retr (st_hor_retr),
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.end_hor_retr (end_hor_retr),
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.vert_total (vert_total),
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.end_vert (end_vert),
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.st_ver_retr (st_ver_retr),
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.end_ver_retr (end_ver_retr),
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.v_retrace (v_retrace),
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.vh_retrace (vh_retrace)
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);
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vga_lcd lcd (
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.clk (wb_clk_i),
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.rst (wb_rst_i),
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.shift_reg1 (shift_reg1),
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.graphics_alpha (graphics_alpha),
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.pal_addr (pal_addr),
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.pal_we (pal_we),
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.pal_read (pal_read),
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.pal_write (pal_write),
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.dac_we (dac_we),
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.dac_read_data_cycle (dac_read_data_cycle),
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.dac_read_data_register (dac_read_data_register),
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.dac_read_data (dac_read_data),
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.dac_write_data_cycle (dac_write_data_cycle),
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.dac_write_data_register (dac_write_data_register),
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.dac_write_data (dac_write_data),
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.csr_adr_o (csr_adr_o),
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.csr_dat_i (csr_dat_i),
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.csr_stb_o (csr_stb_o),
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.vga_red_o (vga_red_o),
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.vga_green_o (vga_green_o),
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.vga_blue_o (vga_blue_o),
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.horiz_sync (horiz_sync),
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.vert_sync (w_vert_sync),
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.cur_start (cur_start),
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.cur_end (cur_end),
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.vcursor (vcursor),
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.hcursor (hcursor),
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.horiz_total (horiz_total),
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.end_horiz (end_horiz),
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.st_hor_retr (st_hor_retr),
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.end_hor_retr (end_hor_retr),
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.vert_total (vert_total),
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.end_vert (end_vert),
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.st_ver_retr (st_ver_retr),
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.end_ver_retr (end_ver_retr),
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.x_dotclockdiv2 (x_dotclockdiv2),
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.v_retrace (v_retrace),
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.vh_retrace (vh_retrace)
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);
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vga_cpu_mem_iface cpu_mem_iface (
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i),
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.wbs_adr_i (wb_adr_i),
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.wbs_sel_i (wb_sel_i),
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.wbs_we_i (wb_we_i),
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.wbs_dat_i (wb_dat_i),
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.wbs_dat_o (mem_wb_dat_o),
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.wbs_stb_i (stb & !wb_tga_i),
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.wbs_ack_o (mem_wb_ack_o),
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.wbm_adr_o (wbm_adr_o),
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.wbm_sel_o (wbm_sel_o),
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.wbm_we_o (wbm_we_o),
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.wbm_dat_o (wbm_dat_o),
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.wbm_dat_i (wbm_dat_i),
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.wbm_stb_o (wbm_stb_o),
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.wbm_ack_i (wbm_ack_i),
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.chain_four (chain_four),
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.memory_mapping1 (memory_mapping1),
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.write_mode (write_mode),
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.raster_op (raster_op),
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.read_mode (read_mode),
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.bitmask (bitmask),
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.set_reset (set_reset),
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.enable_set_reset (enable_set_reset),
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.map_mask (map_mask),
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.read_map_select (read_map_select),
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.color_compare (color_compare),
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.color_dont_care (color_dont_care)
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);
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vga_mem_arbitrer mem_arbitrer (
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.clk_i (wb_clk_i),
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.rst_i (wb_rst_i),
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.wb_adr_i (wbm_adr_o),
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.wb_sel_i (wbm_sel_o),
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.wb_we_i (wbm_we_o),
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.wb_dat_i (wbm_dat_o),
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.wb_dat_o (wbm_dat_i),
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.wb_stb_i (wbm_stb_o),
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.wb_ack_o (wbm_ack_i),
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.csr_adr_i (csr_adr_i),
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.csr_dat_o (csr_dat_i),
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.csr_stb_i (csr_stb_i),
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.csrm_adr_o (csrm_adr_o),
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.csrm_sel_o (csrm_sel_o),
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.csrm_we_o (csrm_we_o),
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.csrm_dat_o (csrm_dat_o),
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.csrm_dat_i (csrm_dat_i)
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);
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// Continous assignments
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assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
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assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
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assign stb = wb_stb_i & wb_cyc_i;
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assign vert_sync = ~graphics_alpha ^ w_vert_sync;
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// Behaviour
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// csr_adr_i
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always @(posedge wb_clk_i)
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csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
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// csr_stb_i
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always @(posedge wb_clk_i)
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csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
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endmodule
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