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155 lines
7.3 KiB
Verilog
Executable File
155 lines
7.3 KiB
Verilog
Executable File
////////////////////////////////////////////////////////////////////////////////
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// Original Author: Schuyler Eldridge
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// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
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// sqrt_pipelined.v
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// Created: 4.2.2012
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// Modified: 4.5.2012
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//
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// Implements a fixed-point parameterized pipelined square root
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// operation on an unsigned input of any bit length. The number of
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// stages in the pipeline is equal to the number of output bits in the
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// computation. This pipelien sustains a throughput of one computation
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// per clock cycle.
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//
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// Copyright (C) 2012 Schuyler Eldridge, Boston University
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module sqrt_pipelined
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(
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input clk, // clock
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input reset_n, // asynchronous reset
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input start, // optional start signal
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input [INPUT_BITS-1:0] radicand, // unsigned radicand
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output reg data_valid, // optional data valid signal
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output reg [OUTPUT_BITS-1:0] root // unsigned root
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);
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// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
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// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
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// OVERWRITTEN!
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parameter
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INPUT_BITS = 16; // number of input bits (any integer)
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localparam
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OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits
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reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation
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reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values
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reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values
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wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values
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// This is the first stage of the pipeline.
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always @ (posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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start_gen[0] <= 0;
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radicand_gen[INPUT_BITS-1:0] <= 0;
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root_gen[INPUT_BITS-1:0] <= 0;
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end
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else begin
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start_gen[0] <= start;
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if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin
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radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];
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root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];
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end
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else begin
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radicand_gen[INPUT_BITS-1:0] <= radicand;
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root_gen[INPUT_BITS-1:0] <= 0;
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end
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end
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end
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// Main generate loop to create the masks and pipeline stages.
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generate
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genvar i;
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// Generate all the mask values. These are built up in the
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// following fashion:
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// LAST MASK: 0x00...001
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// 0x00...004 Increasing # OUTPUT_BITS
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// 0x00...010 |
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// 0x00...040 v
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// ...
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// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS
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//
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// Note that the first mask used can either be of the 0x1... or
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// 0x4... variety. This is purely determined by the number of
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// computation stages. However, the last mask used will always be
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// 0x1 and the second to last mask used will always be 0x4.
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for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4
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if (i % 2) // i is odd, this is a 4 mask
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assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);
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else // i is even, this is a 1 mask
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assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);
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end
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// Generate all the pipeline stages to compute the square root of
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// the input radicand stream. The general approach is to compare
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// the current values of the root plus the mask to the
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// radicand. If root/mask sum is greater than the radicand,
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// subtract the mask and the root from the radicand and store the
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// radicand for the next stage. Additionally, the root is
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// increased by the value of the mask and stored for the next
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// stage. If this test fails, then the radicand and the root
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// retain their value through to the next stage. The one weird
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// thing is that the mask indices appear to be incremented by one
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// additional position. This is not the case, however, because the
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// first mask is used in the first stage (always block after the
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// generate statement).
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for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline
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always @ (posedge clk or negedge reset_n) begin : pipeline_stage
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if (!reset_n) begin
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start_gen[i+1] <= 0;
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radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
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root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
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end
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else begin
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start_gen[i+1] <= start_gen[i];
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if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] +
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mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin
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radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] -
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mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] -
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root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
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root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) +
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mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];
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end
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else begin
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radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
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root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;
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end
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end
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end
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end
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endgenerate
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// This is the final stage which just implements a rounding
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// operation. This stage could be tacked on as a combinational logic
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// stage, but who cares about latency, anyway? This is NOT a true
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// rounding stage. In order to add convergent rounding, you need to
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// increase the input bit width by 2 (increase the number of
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// pipeline stages by 1) and implement rounding in the module that
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// instantiates this one.
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always @ (posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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data_valid <= 0;
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root <= 0;
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end
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else begin
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data_valid <= start_gen[OUTPUT_BITS-1];
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if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])
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root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;
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else
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root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];
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end
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end
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endmodule
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