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78 lines
2.1 KiB
Verilog
Executable File
78 lines
2.1 KiB
Verilog
Executable File
////////////////////////////////////////////////////////////////////////////////
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// Original Author: Schuyler Eldridge
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// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
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// t_sqrt_pipelined.v
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// Created: 4.2.2012
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// Modified: 4.5.2012
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//
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// Testbench for generic sqrt operation
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//
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// Copyright (C) 2012 Schuyler Eldridge, Boston University
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module t_sqrt_pipelined();
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parameter
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INPUT_BITS = 4;
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localparam
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OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
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reg [INPUT_BITS-1:0] radicand;
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reg clk, start, reset_n;
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wire [OUTPUT_BITS-1:0] root;
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wire data_valid;
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// wire [7:0] root_good;
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sqrt_pipelined
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#(
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.INPUT_BITS(INPUT_BITS)
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)
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sqrt_pipelined
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(
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.clk(clk),
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.reset_n(reset_n),
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.start(start),
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.radicand(radicand),
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.data_valid(data_valid),
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.root(root)
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);
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initial begin
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radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
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#10 reset_n = 0; clk = 0;
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#50 reset_n = 1; radicand = 0;
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// #40 radicand = 81; start = 1;
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// #10 radicand = 16'bx; start = 0;
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#10000 $finish;
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end
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always
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#5 clk = ~clk;
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always begin
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#10 radicand = radicand + 1; start = 1;
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#10 start = 0;
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end
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// always begin
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// #80 start = 1;
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// #10 start = 0;
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// end
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endmodule
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