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			87 lines
		
	
	
		
			1.5 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			87 lines
		
	
	
		
			1.5 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
/*
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*
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* Copyright (c) 2011 fpgaminer@bitcoin-mining.com
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*
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program.  If not, see <http://www.gnu.org/licenses/>.
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* 
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*/
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`timescale 1ns/1ps
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module e0 (x, y);
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	input [31:0] x;
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	output [31:0] y;
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	assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
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endmodule
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module e1 (x, y);
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	input [31:0] x;
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	output [31:0] y;
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	assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
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endmodule
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module ch (x, y, z, o);
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	input [31:0] x, y, z;
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	output [31:0] o;
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	assign o = z ^ (x & (y ^ z));
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endmodule
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module maj (x, y, z, o);
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	input [31:0] x, y, z;
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	output [31:0] o;
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	assign o = (x & y) | (z & (x | y));
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endmodule
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module s0 (x, y);
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	input [31:0] x;
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	output [31:0] y;
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	assign y[31:29] = x[6:4] ^ x[17:15];
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	assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
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endmodule
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module s1 (x, y);
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	input [31:0] x;
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	output [31:0] y;
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	assign y[31:22] = x[16:7] ^ x[18:9];
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	assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
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endmodule
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