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50 lines
1.6 KiB
Verilog
Executable File
50 lines
1.6 KiB
Verilog
Executable File
////////////////////////////////////////////////////////////////////////////////
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// Original Author: Schuyler Eldridge
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// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
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// sign_extender.v
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// Created: 5.16.2012
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// Modified: 5.16.2012
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//
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// Generic sign extension module
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//
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// Copyright (C) 2012 Schuyler Eldridge, Boston University
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns/1ps
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module sign_extender
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#(
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parameter
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INPUT_WIDTH = 8,
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OUTPUT_WIDTH = 16
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)
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(
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input [INPUT_WIDTH-1:0] original,
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output reg [OUTPUT_WIDTH-1:0] sign_extended_original
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);
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wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
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generate
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genvar i;
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for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
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assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
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end
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endgenerate
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always @ * begin
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sign_extended_original = {sign_extend,original};
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end
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endmodule
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