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Add common Verilog extensions

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This commit is contained in:
Dan Luu
2013-10-25 20:54:58 -05:00
parent ce6a8aa671
commit 7b1c78b848
1 changed files with 6 additions and 0 deletions
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6
lib/linguist/languages.yml
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@@ -1421,6 +1421,12 @@ Verilog:
extensions: extensions:
- .sv - .sv
- .svh - .svh
- .tf
- .tfi
- .tft
- .tfw
- .veo
- .vf
- .vh - .vh
VimL: VimL: