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Merge pull request #741 from danluu/verilog_extensions

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Add common Verilog extensions
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Ted Nyman
2013-11-05 15:23:38 -08:00
parent 6fb4e6836c 7b1c78b848
commit c1e38425d0
1 changed files with 6 additions and 0 deletions
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6
lib/linguist/languages.yml
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@@ -1524,6 +1524,12 @@ Verilog:
extensions: extensions:
- .sv - .sv
- .svh - .svh
- .tf
- .tfi
- .tft
- .tfw
- .veo
- .vf
- .vh - .vh
VimL: VimL: