Enable Verilog lexer

2026-01-01 23:16:16 +00:00 · 2011-09-26 11:31:24 -05:00
parent e04df8dda2
commit c6896d6338
1 changed files with 1 additions and 1 deletions
--- a/lib/linguist/languages.yml
+++ b/lib/linguist/languages.yml
@@ -969,7 +969,7 @@ Vala:

 Verilog:
  type: programming
-  lexer: Text only
+  lexer: verilog
  extensions:
  - .v