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Enable Verilog lexer

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This commit is contained in:
Joshua Peek
2011-09-26 11:31:24 -05:00
parent e04df8dda2
commit c6896d6338
1 changed files with 1 additions and 1 deletions
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lib/linguist/languages.yml
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@@ -969,7 +969,7 @@ Vala:
Verilog: Verilog:
type: programming type: programming
lexer: Text only lexer: verilog
extensions: extensions:
- .v - .v